1.DSP
Design Using AccelDSP Synthesis
Course Description
This is a 2 day course to learn how to synthesize
an algorithm written in MATLAB into a design that is optimized
for a Xilinx FPGA. Learn how to take MATLAB coding changes
that improve area and performance. Use the floating- to
fixed-point and design exploration features of the Accel
DSP Synthesis Tool to achieve maximum results. Learn how
to merge a synthesized MATLAB block into a larger HDL design
or System Generator design.
Duration
2 days
Course Outline
Module 1 : Introducing Accel DSP
Lab 1 – Get Started
Module 2: Synthesizable MATLAB
Lab 2 – Synthesizable MATLAB
Module 3: Quantization
Lab 3 – Quantization
Module 4: Multi-Rate Design
Lab 4 – Multi-Rate Design
Module 5: Using AccelWare
Lab 5 – Using AccelWare
Module 6: Design Exploration
Lab 6 – Design Exploration
Module 7: Adding Hardware Control
Lab 7 – Adding Hardware Control
Module 8: Coding for Hardware Performance
Lab 8 – Coding for Hardware Performance
Module 9: Interfacing to System Hardware
Lab 9 – Interfacing to System Hardware
Module 10: Exporting to System Generator
Lab 10 – Exporting to System Generator
2.DSP Implementation
Techniques for Xilinx FPGAs
Course Description
This 3 days practical workshop is designed to close the
gap between DSP system designers and hardware developers.
As well as explaining how DSP algorithms can be efficiently
implemented, it also shows how decisions at system level
can influence both the development process and the product
costs. This workshop is thus aimed at developers who are
familiar with product developments requiring digital signal
processing. The focus will be on system design, hardware
design and DSP algorithms. The theoretical content will
be rounded off with exercises on the laptop/PC.
Duration
3 days
Who Must Attend
Engineers and designers who have an interest in developing
products that use digital signal processing
Prerequisites
Although the workshop begins with a brief outline of the
basic DSP theory, you should have a fundamental knowledge
of the following areas:
- Scanning frequencies and FIR (Finite Impulse Response)
and IIR (Infinite Impulse Response) filter
- Oscillators, mixers and FFT (Fast Fourier Transformation)
algorithms.
Why this training pays huge dividends
After completing this training, you will be able to:
- Describe how DSP algorithms can be efficiently implemented
using Xilinx FPGA technology
- Establish methods for the accurate estimation of silicon
area consumed and hence costs
- Evaluate which algorithms are best suited to FPGA implementation
and understand which algorithms are less desirable
- Observe how system level decisions impact the hardware
implementation, and that the hardware implementation can
enhance the results at the system level
- Investigate the use of Xilinx CORE Generator to realize
typical DSP algorithms
Course Outline
“Being on the same wavelength”
- Basic terminology and acronyms used in DSP design
- Sample rates and bit widths used in DSP applications
- DSP building blocks and processing requirements
“Some bits about numbers”
- Numbering formats, range and precision
- Mathematical operations using a variety of formats
“Tuning the receiver”
- Structure and resources of XILINX devices
- Estimating DSP building block sizes & Implementing
the multiplication function
- Bit width impact on system level decisions
“Memories are made of This”
- Block versus distributed memory
- Memory aspect ratios and their manipulation
- SRL16E and the delay function
“Selective Filters”
- FIR filter specifications and implementations & Selection
of a technique for a given specification
- Effects of halfband and interpolated filters
- Creating an SDA FIR filter with Core Generator
“One filter doesn't make a system”
- Rate changing and how it effects FIR filter choice
- Filtering algorithms that exploit device architecture
- Importance of connectivity versus isolated functions
“Don’t block the data path”
- Strategies for FFT implementation
- Achieving bandwidth requirements of the FF
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3.DSP design courses
DSP Design Flow
Course Description
The DSP Design Flow course provides the advanced tools and
expertise you need to develop more advanced, low-cost DSP
designs. This intermediate course in implementing DSP functions
focuses on learning how to use System Generator for DSP, as
well as HDL design flow, CORE Generator™ software, design
implementation tools, and hardware in the loop verification.
Through hands-on exercises, you will implement a design from
algorithm concept to hardware verification using Xilinx FPGA
capabilities.
Level
- Intermediate
Duration
- 3 days
Who Must Attend
System engineers and designers, logic designers, and experienced
hardware engineers who areimplementing DSP algorithms using
MathWorks® MATLAB and Simulink™ and using the Xilinx
System Generator for DSP.
Prerequisites
- Fundamentals of MATLAB/Simulink and Xilinx FPGAs
- Basics of digital signal processing theory for functions
such as FIR (Finite Impulse Response) filters, oscillators
and mixers, and FFT (Fast Fourier Transform) algorithms
Why this training pays huge dividends
- Make cost-versus-performance tradeoffs early in the design
process, and use bit- and cycle-true simulations in Simulink
- Understand how decisions made in the Simulink environment
impact the size of the FPGA design
- Understand the strengths and weaknesses of three design
flows (HDL, CORE Generator, System Generator)
- Implement a design from start to finish using the System
Generator
- Understand the hardware in the loop-accelerated verification
Software Tools
- ISE
- System Generator for DSP
Mentor Graphics® ModelSim™
Course Outline
Day 1 DSP Design Implementation Tools
- Agenda
- Introduction
- DSP Design Flows in FPGAs
- Lab 1: Creating a 12 x 8 MAC Using VHDL
- Lab 2: Creating a 12 x 8 MAC Using the Xilinx CORE Generator
System
- Lab 3: Creating a 12 x 8 MAC Using the Xilinx System Generator
Day 2 Digital Signal Processing Functions
- Digital Filtering
- Lab 4: Designing a FIR Filter
- HDL Co-Simulation
- Lab 5: MAC FIR Filter Verification Using Co-Simulations
- Looking Under the Hood
- Lab 6: Looking Under the Hood
- Controlling the System
- Lab 7: Controlling the System
Day 3 Digital Signal Processing Functions
- Multi-rate Systems
- Lab 8: Designing a MAC FIR
- Advanced Features
- Lab 9: Designing Using the PicoBlaze™ Microcontroller
- Lab 10: Creating Parametric Designs
- Wrap up
LAB DESCRIPTIONS
This lab-intensive class gives you hands-on experience using
the System Generator for DSP to visualize, simulate, verify,
and implement DSP algorithms in Xilinx FPGAs. The labs start
at a descriptive level and build on each other. You can expect
each successive lesson's challenges to increase. Many new
System Generator for DSP 6.1 features are identified, and
a few demonstrations are presented to illustrate the strengths
of the new features in improving productivity using hardware
in the loop accelerated verification.
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