ASIC developments in digital CMOS (complimentary
metal oxide semiconductor) technologies are the most common
microelectronics pursuit. They are suited to medium to high
levels of production where NRE costs may be recouped by production
cost savings due to lower component counts or lower per part
costs.
Timing driven design flow
A timing driven design flow (TDD) is suitable for fabrication
technologies of 0.25 micron and above. The Register Transfer
Language (RTL) is synthesized to a symbolic implementation
in terms of logic gates and a netlist, which is then implemented
with a separate physical place and route stage. The separation
of these activities means that estimates of wire delays need
to be supplied to the synthesis tool. Satisfying timing constraints
becomes more difficult if this methodology is employed for
finer line, deep sub-micron technologies.
A deep sub-micron (DSM) design flow addresses a number of
physical effects that arise as the fabrication technology
moves below 0.18 micron. Signal integrity becomes the central
issue because the inter-line capacitance (that is wire to
wire) becomes more dominant than the line to substrate capacitance,
causing cross talk and interference between signals. At the
same time the fine line technology produces narrower wires,
which are more resistive, and the drive strength of the transistors
in the logic gates is reduced as less transistor area is used.
The net result is that interconnect can no longer be considered
as ideal and the signal propagation delay due to interconnect
can be more significant than the gate delay.
Design complexities rise as larger, more complex systems can
be integrated into fine line technologies. This complexity
has a large impact on design testability and practices that
Design for Test (DFT) must be employed. Demands for faster
clock speeds and lower power push design techniques to the
limit of the time.
