An analog design flow can be broken into two
parts; one for large analog systems where analog modules are
assembled, and another for generation of the individual analog
modules. Issues such as reduced noise immunity, a greater dependence
on device matching and process variation means that most analog
implementations require manual design (no synthesis) and manual
layout. With less automation available, analog design practices
turn to hierarchy management and modular design practices to
cope with increasing complexity.
The physical implementation affects circuit performance to a
far greater extent than in digital circuits. Consequently, synthesis
of analog circuits has not progressed very far and analog implementations
are substantially manual pursuits.
Process variation in manufacture can impact heavily on performance
and yield. Circuit design needs to use process tolerant topologies
and process variation needs to be allowed for during simulation.
Design portability (between fabrication facilities) is reduced
for the same reason.
A Mixed Signal
IC is appropriate for small and medium sized chips (<250,000
transistors), where a combination of analog and digital circuitry
is integrated. Such designs are generally partitioned into analog
and digital sections and then handled with design flows appropriate
for each section. The analog module design flow is usually appropriate
for analog sections of the chip and includes the generation
of AMS models, which can be used in full chip verification suites.
The digital section of the chip can then proceed using a timing
driven design flow or a deep sub micron design flow as appropriate.
To differentiate it from SoC development, this mixed signal
design flow refers to chips up to 250,000 transistors and, as
such, a timing driven digital design flow has been featured.
The Mixed Signal IC inherits the key issues involved with both
digital and analog design flows. System level verification of
a mixed signal design requires specialized techniques and tools,
especially at the interface boundary between analog and digital
circuits.
